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Synchronous OEIC integrating receiver for optically reconfigurable gate arrays
Sánchez Azqueta, Carlos
(Universidad de Zaragoza)
;
Goll, B.
;
Celma Pueyo, Santiago
(Universidad de Zaragoza)
;
Zimmermann, H.
Resumen:
A monolithically integrated optoelectronic receiver with a low-capacitance on-chip pin photodiode is presented. The receiver is fabricated in a 0.35µm opto-CMOS process fed at 3.3V and due to the highly effective integrated pin photodiode it operates at µW. A regenerative latch acting as a sense amplifier leads in addition to a low electrical power consumption. At 400 Mbit/s, sensitivities of -26.0dBm and -25.5dBm are achieved, respectively, for ¿ = 635nm and ¿ = 675nm (BER =10-9) with an energy efficiency of 2 pJ/bit.
Idioma:
Inglés
DOI:
10.3390/s16060761
Año:
2016
Publicado en:
SENSORS
16, 6 (2016), 761
ISSN:
1424-8220
Financiación:
info:eu-repo/grantAgreement/ES/MEC/CAS14-00326
Financiación:
info:eu-repo/grantAgreement/ES/MINECO/TEC2011-23211
Financiación:
info:eu-repo/grantAgreement/ES/MINECO/TEC2014-52840-R
Tipo y forma:
Article (Published version)
Área (Departamento):
Electrónica
(
Departamento de Ingeniería Electrónica y Comunicaciones
)
You must give appropriate credit, provide a link to the license, and indicate if changes were made. You may do so in any reasonable manner, but not in any way that suggests the licensor endorses you or your use.
0
Exportado de SIDERAL (2017-01-17-13:22:03)
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Record created 2017-01-17, last modified 2017-01-17
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